The present invention relates generally to logic circuits, and more particularly to an apparatus for a current mode logic circuit with a variable delay.
When high-speed and low voltage swing data transfer is needed, differential signaling (also commonly referred to as double ended signals) is perhaps the most robust and promising signaling concept. Current mode logic (CML), a design technique commonly used in high speed signaling applications such as communications chips and routers, uses differential signaling.
CML is widely used in high-speed applications due to its relatively low power consumption and low supply voltage when compared to other types of logic, such as emitter coupled logic (ECL). CML is also considerably faster than CMOS due to its lower voltage swings. CML also has an added advantage of the capability of being fabricated using CMOS fabrication technology.
A common situation that arises in circuit design is timing mismatches between various signals in the circuit, when the signals are needed to occur at essentially the same time. However, due to an unbalanced number of gate delays and/or variations in the fabrication of transistors and logic gates, signals that are to occur simultaneously can often occur with significant amounts of time elapsed between them.
One solution that can be used to fix timing mismatches between various signals in a circuit is to add extra gate delays to the signal path of the signal that is occurring earlier than the other signal. The gate delay can be in the form of circuit elements such as buffer stages, double inverters, and so forth. These circuit elements have differing delays associated with them, depending upon the relative complexity (such as the number of transistors and/or memory elements in the signal path) of the circuit elements. Multiple circuit elements can be cascaded and then selectively enabled/disabled to achieve a proper timing match between the signals.
Another solution that can be used to fix timing mismatches involves the use of latches on the signal paths. The latches then can capture the value on the signal paths, thus synchronizing the signals to a clock that is used to clock the latches. Each latched signal occurs at the same time and in synchrony with the latch clock.
One disadvantage of the prior art is the use of circuit elements to introduce gate delays imparts a fixed amount of delay. Therefore, if the delay that needs to be corrected is a fraction of a minimum gate delay, the delay cannot be corrected.
A second disadvantage of the prior art is that the amount of delay imparted by the circuit elements can themselves change depending on fabrication variances. Therefore, the circuit elements cannot be counted upon to provide a consistent amount of delay across different circuits.
A third disadvantage of the prior art is that the use of latches to synchronize signals does not work well with circuits whose signals are intended to be asynchronous in nature. This means that the signal transitions may arrive at unpredictable times that may be missed by the latches. If signal transitions are missed by the latches, then important information carried on the signals is lost.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which presents an apparatus for introducing a variable delay in a current mode logic circuit.
In accordance with a preferred embodiment of the present invention, a current mode logic (CML) variable delay element comprising a buffer having an input coupled to an input signal, the buffer to insert a fixed delay to the input signal, a multiplexer having a first input coupled to the input signal and a second input coupled to an output of the buffer, the multiplexer containing circuitry to provide a voltage measured at its inputs to a multiplexer output, and a multiplexer control signal line coupled to a multiplexer control input, the multiplexer control signal line used to carry a multiplexer control signal to proportionally combine the voltage at the multiplexer""s inputs and provide it at the multiplexer output.
In accordance with another preferred embodiment of the present invention, a current mode logic (CML) variable delay element comprising a buffer having an input coupled to a input signal, the buffer to insert a fixed delay to the input signal, a multiplexer having first input coupled to the input signal and a second input coupled to an output of the buffer, the multiplexer containing circuitry combine a first voltage on its first input and a second voltage on its second input to produce an output signal that is a delayed version of the input signal, and a multiplexer control signal line coupled to a multiplexer control input, the multiplexer control signal line used to carry a multiplexer control signal to specify a delay imparted upon the input signal.
An advantage of a preferred embodiment of the present invention is that the capability to produce a variable delay enables an arbitrary timing mismatch between signals to be corrected.
A further advantage of a preferred embodiment of the present invention is that multiple variable delay elements can be cascaded to enable a delay period that is greater than possible with a single variable delay element.
Yet another advantage of a preferred embodiment of the present invention is that the delay imparted by the variable delay element is relatively independent of manufacturing differences. Therefore, differences in delay by different variable delay elements that are used on different circuits can be easily compensated for through the ability to vary the delay.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.